1. Field of the Invention
The technical field of this invention lies with tristate output buffer circuits utilized to coupled a multiplicity of logic circuits to a common bus. More particularly, this invention is related to providing pullup transistor breakdown protection for a buffer in its inactive mode without compromising high-to-low output transition times for the same buffer in its active mode. More particularly yet, this invention provides two different paths for discharging the base node of the output pullup transistor of said buffer circuit such that the operative discharge path for the buffer's high Z (inactive mode) provides extra protection against reverse breakdown of said output pullup transistor while the operative discharge path of said buffer in its active state is free of extraneous capacitance which would slow H.fwdarw.L output switching.
In its preferred embodiment, the State-Dependent Discharge Path Circuit of the present invention is incorporated into tristate BiCMOS circuits and is comprised of CMOS transistors serving to protect and enhance the operation of bipolar output pullup transistors. More particularly, the preferred embodiment comprises an improvement to the BiCMOS output buffer circuit described in the related patent application identified above and described below. Such output buffer circuits incorporate the low power requirements, high input impedance, and high speed advantages of MOSFET transistors such an NMOS and PMOS transistors along with the high current amplification and low output impedance advantages of bipolar transistors such an NPN transistors.
2. Description of Related Art
A non-inverting BiCMOS output buffer circuit according to the related patent application identified above is illustrated in FIG. 1. This is a tristate buffer, with the enable circuit having complementary enable signal inputs E and EB. Enable signal input E is coupled to a CMOS pullup enable stage Q16,Q13 and complementary enable signal input EB is coupled to a CMOS pulldown enable stage Q12,Q9. The pullup enable stage Q16,Q13 is coupled in a NAND gate with a pullup-predriver-input-inverter-stage Q15,Q14; the pulldown enable stage Q12,Q9 is coupled in a NOR gate with a pulldown-predriver-input-inverter stage Q11,Q10. As will be discussed subsequently, biasing enable input E with a logic high signal (and the complementary input EB with a logic low signal) places the output buffer in its bistate active mode controlled by V.sub.IN. Conversely, biasing E low and EB high places the output buffer in its inactive mode (the high Z state) and not subject to V.sub.IN. The discussion immediately following of the circuit depicted in FIG. 1 assumes that the complementary enabling inputs E, EB are biased so as to place the buffer in its active mode. In that mode, transistors Q16 and Q9 are non-conducting and transistors Q13 and Q12 are conducting.
In its active mode, the BiCMOS output buffer circuit delivers output signals of high and low potential levels H, L at the output V.sub.OUT in response to data signals at the input V.sub.IN. Specifically, a logic high input at V.sub.IN, after passing through a double inversion predriver circuit comprised of CMOS transistors, triggers a Darlington bipolar output pullup transistor pair Q24, Q22 so as to source current from the high potential output supply rail V.sub.CCN through resistor R6 and diode D1 coupled to the collector node of bipolar output pullup transistor Q22 to the output V.sub.OUT. Similarly, a logic low input at V.sub.IN, after passing through the inverting predriver circuit Q11,Q10 turns on high current capacity output pulldown transistor pair Q44A,Q44B, so that they sink current from the output V.sub.OUT to the low potential output ground rail GNDN.
More precisely and with continuing reference to FIG. 1, the input V.sub.IN is coupled directly to a CMOS pullup-driver-circuit comprising pullup-predriver-input-inverter-stage Q15,Q14 and, through intermediate node n1, to a pullup-driver-inverter-stage Q21A,Q20. This second inverter stage Q21,Q20 is coupled to the base nodes of bipolar output pullup transistors Q24,Q22. A logic high data signal H at the input V.sub.IN thus causes the pullup-driver-inverter-stage PMOS transistor Q21A to provide base drive current to bipolar transistor Q24. Bipolar transistor Q24, coupled via its collector node to the output supply rail V.sub.CCN through Schottky diode SD1 and resistor R5, in turn sources amplified base drive current to bipolar output pullup transistor Q22.
In contrast, a logic low data signal L at the input V.sub.IN, causes the pullup-driver-inverter-stage NMOS transistor Q20 to couple the base of bipolar output pullup transistor Q24 directly to GNDQ and the base of bipolar output pullup transistor Q22 to GNDQ through the forward-biased Schottky diode pair SD11,SD12 in series-thus turning off both pullup transistors.
With continuing reference to FIG. 1, V.sub.in is also coupled to a CMOS pull-down-predriver-input-inverter stage Q11,Q10 and, through intermediary node n2, to a control gate node of pulldown driver transistor Q60, an NMOS transistor. Transistor Q60 is coupled to the base node of the bipolar output-pulldown-transistor Q44, actually a pair of high-current-capacity transistors Q44B,Q44A. The pulldown driver transistor Q60 source is coupled to the high potential power rail V.sub.CCQ through diode SD3 and resistor R4 so that when it is conducting, is sources drive current to the base node of bipolar output pulldown transistor Q44. Transistor Q60 is an effective "phase splitter," operating bipolar output pulldown transistor Q44 out of phase with bipolar output pullup transistor Q22.
The pulldown driver stage also includes a "Miller Killer" (MK) transistor Q9A coupled for sinking parasitic Miller capacitance current from the base node of bipolar pulldown transistor Q44 to the output ground GNDN. An MK predriver stage Q40,Q41 is coupled between the common node n2 of the pulldown predriver input stage Q11,Q10 and the control gate node of the MK transistor Q9A. The small-current-conducting MK transistor Q9A and the two MK predriver stage transistors Q40,Q41 are all constructed with small channel widths so as to enhance switching speed. The operation of MK transistor Q9A is sufficiently fast that it operates as an AC Miller Killer (ACMK) during H to L transitions at the output V.sub.out as well as a DC Miller Killer (DCMK) transistor during steady-state high Z operation, guarding against Miller Current effects when the output V.sub.out is forced high by events occurring elsewhere on the common bus.
An accelerating feedback diode SD4 is coupled between the output V.sub.out and the drain node of pulldown driver transistor Q60. Discharge current from the output V.sub.out is therefore fed back through the primary current path of this NMOS pulldown driver transistor Q60 in order to accelerate turn-on of the bipolar output pulldown transistor pair Q44 during a H.fwdarw.L output transition.
The previous discussion assumed that enable inputs E and EB were biased so as to maintain the buffer in its active bistate, under the control of V.sub.IN. That required a logic high signal at E and the complementary logic low at EB. Conversely, if E is given a logic low signal, transistor Q16 will become conducting. When that happens transistor Q21A will have a logic high bias at its control gate and hence will be incapable of providing base drive to pullup transistor Q24 regardless of whether transistor Q15 is on or off. Thus, with E low, there will be no current-sourcing regardless of the signal applied to the input V.sub.IN. Similarly, the complementary logic high signal at EB will maintain transistor Q12 off and transistor Q9 on. This means that transistor Q60 will remain off regardless of whether transistor Q11 is conducting. With Q60 off, there will be no base drive for pulldown (current-sinking) transistor Q44. Hence, with EB high, there will be no current sinking regardless of the signal applied to the input V.sub.IN. Therefore, with E low, EB high, both the output pullup transistor Q22 and the twin output pulldown transistor Q44 will appear to the common bus as simply high dc impedances isolating the common bus connection at V.sub.OUT from both the high potential power rail V.sub.CCN and the low potential power rail GNDN. This is what constitutes the inactive mode--also known as the high Z state, the third state, or the "tristate"--of the tristate output buffer.
Normally, all but one of the output buffer circuits coupled to the common bus will be inactive at any instant. Nevertheless, the inactive buffers will still be exposed to the fluctuating potential of the bus through the coupling at V.sub.OUT, and--as indicated above--each inactive buffer will have its output forced high and low by the bus. If precautions are not taken, it is possible for a high voltage appearing at V.sub.OUT to cause reverse breakdown of the emitter-base junction of transistor Q22 and a coupling of the bus to ground through the conducting transistor Q20, with severe bus loading as the consequence. Placing the Schottky diode pair SN11,SD12 in series with the link coupling the base of Q22 to GNDQ boosts the total voltage required for Q22 breakdown by twice the amount of the forward drop of a conducting Schottky diode. Given the voltage required for reverse breakdown in Q22 and the maximum anticipated voltage to which V.sub.OUT will be forced by the bus, this increment is enough to ensure that such reverse breakdown will not occur.
Although the related invention described above and depicted in FIG. 1 meets high switching time and breakdown specifications, it is slowed somewhat in its H.fwdarw.L output switching due to the Schottky diode pair SD11,SD12 added as breakdown protection to the base discharge path of pullup transistor Q22. The capacitance of these diodes provides charge storage which delays the pulling of the output pullup transistor base needed to switch that transistor from conducting to non-conducting. This not only increases the time needed to effect the output transition of the buffer from a current-sourcing (H) to a current-sinking (L) state, but can result in the pullup transistor continuing to source current even after the pulldown transistor has begun to sink current-a simultaneous conduction leading to "crowbar current" losses. Stated differently, the cost of the breakdown protection provided by SD11,SD12 is an increased high-to-low propagation time tp.sub.HL.
What is needed, therefore, is a circuit which, while providing breakdown protection for a inactive tristate buffer with its output forced high, will do so without compromising the H.fwdarw.L switching time of the buffer in its active state.